Embodiments of the present invention relate to data communication, and more particularly to packet-based communication.
Most computer systems are formed of components coupled together using one or more buses, which are used to transmit information between the various system components. Present bus standards such as the Peripheral Component Interconnect (PCI) Specification, Rev. 2.1 (published Jun. 1, 1995) provide a multi-drop bus in which multiple devices are coupled to the same bus. Accordingly, it is easy to read or write to devices on the same bus.
However, as bus interface speeds increase, bus architectures are moving away from multi-drop architectures towards point-to-point architectures. In point-to-point architectures, peer-to-peer communication becomes more difficult as synchronization, ordering, and coherency of such communications becomes more difficult. One example of a point-to-point architecture is a PCI Express™ architecture in accordance with the PCI Express Base Specification, Rev. 1.0 (published Jul. 22, 2002).
Communication between serially connected devices typically involves buffering data to be sent in a transmitting device and then sending the data in a packetized form to a receiving device. Various flow control schemes exist to control the transfer of data between the devices. However, common schemes consume significant resources and can lead to inefficiencies in data transmission as well as consumption of buffer resources, communication delays and the like. Accordingly, a need exists for improved flow control between devices.